Method of forming metal interconnection using plating and semiconductor device manufactured by the method

ABSTRACT

A method is provided for forming a metal interconnection using a plating process, which can improve the throughput and reliability of semiconductor devices by decreasing the required polishing in a chemical mechanical polishing process. A semiconductor device manufactured by this method is also provided. In the method of forming a metal interconnection, a recess region is formed in a portion of an insulation layer formed over a substrate, i.e., where a metal interconnection layer will be formed. A diffusion prevention layer is formed over the substrate, the insulation layer, and the recess region. Then, a metal seed layer is formed over the diffusion prevention layer only in the recess region using a chemical mechanical polishing process or an etch back process. A conductive plating layer is then formed on the metal seed layer only in the recess region. Thereafter, surface planarization is performed to form a metal interconnection layer in the recess region. The plating layer may be formed after forming the seed layer only in the bottom portion of the recess region.

[0001] This application relies for priority upon Korean PatentApplication Nos. 99-39548 and 00-42153, filed on Sep. 15, 1999, and Jul.22, 2000, respectively, the contents of which are herein incorporated byreference in their entirety.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a method of forming a metalinterconnection using plating and a semiconductor device manufactured bythe method. More particularly, the present invention relates to a methodfor manufacturing a metal interconnection in a semiconductor devicehaving a damascene structure and a semiconductor device manufactured bysuch a method.

[0003] In order to reduce RC delay time in a semiconductor device, amethod has been studied of forming a metal interconnection layer usingmetal such as copper, which has a low resistivity. A reduction in RCdelay time is particularly useful in logic devices that require a highoperation speed.

[0004] In one method of forming a metal interconnection material, ametal interconnection material, such as aluminum, is formed over theentire surface of a substrate and the resultant structure is patternedby a conventional photolithography process. However, a different methodis used when forming a metal interconnection layer with copper (Cu) as ametal interconnection material because it is difficult to perform apatterning process with respect to copper. In order to form a metalinterconnection layer using this process, a region where a metalinterconnection is to be made is formed in an insulation layer on asubstrate in advance, and then this area is filled with a metalinterconnection material. A so-called “damascene” process is used toachieve this method.

[0005]FIGS. 1 through 3 are sectional views for explaining a method offorming a metal interconnection of a semiconductor device having aconventional line damascene structure. In the line damascene structure,a trench having a predetermined depth from the surface of an insulationlayer is formed in a line, and a metal interconnection layer is formedin the trench. A method of forming a metal interconnection of a linedamascene structure will now be described with reference to the attacheddrawings.

[0006] Referring to FIG. 1, a trench region 11 of a line shape is formedby performing a photolithography process on an insulation layer 10,which is formed over a substrate 5. Subsequently, a diffusion preventionlayer 12 is formed over the entire surface of the insulation layer 10,including the trench region 11. Next, copper is deposited over thediffusion prevention layer 12 by a physical vapor deposition (PVD)method such as sputtering, thereby forming a seed layer 14.

[0007] Referring to FIG. 2, a plating layer 16 of copper is then formedover the resultant structure, including the seed layer 14, using anelectroplating method. The plating layer 16 is formed thick enough tocompletely fill the trench region 11.

[0008] Referring to FIG. 3, some of the plating layer 16 is then removedby a chemical-mechanical polishing (CMP) process until a portion of theinsulation layer 10 is exposed. As a result of this, remaining portionsof the diffusion prevention layer 12 and the seed layer 14, as well as ametal interconnection layer 16 a that is formed from the portion of theplating layer 16 remains within each trench region 11, in the vicinityof the surface of the insulation layer 10.

[0009]FIGS. 4 through 7 are a plan view and section views for explaininga method of forming a metal interconnection of a semiconductor devicehaving a conventional dual damascene structure. In the dual damascenestructure, a metal interconnection formed to fill a trench region of aline shape is combined with a contact filling a contact hole or avia-hole in order to connect to an underlying conductive layer. A methodof forming a metal interconnection of a dual damascene structure will bedescribed below.

[0010] Referring to FIG. 4, lower conductive layers 28 are formed over asubstrate 5 at a predetermined interval. Metal interconnection layers 26a are formed over the lower conductive layers 28 at anotherpredetermined interval. An insulation layer (not shown in FIG. 4) isinterposed between the metal interconnection layer 26 a and theunderlying lower conductive layer 28. The metal interconnection layer 26a is electrically connected to the underlying lower conductive layer 28through a contact hole region 30. FIGS. 5 through 7 are sectional viewsof FIG. 4 taken along the line VII-VII′, and show the sequential stepsof fabricating the device of FIG. 4.

[0011] Referring to FIG. 5, a conductive material is deposited andpatterned over a substrate 15 to form lower conductive layers 28 atregular intervals. Subsequently, an insulation layer 20 is formed overthe entire surface of the resultant structure, including the lowerconductive layers 28. A typical photolithography process is thenperformed on the insulation layer 20 to form a contact hole region 30and a trench region 31 that includes the contact hole region 30. Next, adiffusion prevention layer 22 and a seed layer 24 are sequentiallyformed over the entire surface of the resultant structure, including thecontact hole region 30 and the trench region 31.

[0012] Referring to FIG. 6, the substrate 15 over which the seed layer24 is formed is then loaded into an electroplating apparatus and iselectroplated to form a plating layer 26 of copper.

[0013] Referring to FIG. 7, the surface of the substrate 15, includingthe plating layer 26, is then planarized by a chemical mechanicalpolishing (CMP) process. This surface planarization is performed on theplating layer 26, the seed layer 24, and the diffusion prevention layer22 until the surface of the insulation layer 20 is exposed. In this waya metal interconnection layer 26 a is formed that has a dual damascenestructure and a planarized surface, as shown in FIG. 7.

[0014] However, the method described above of forming a metalinterconnection having a line or dual damascene structure has severalproblems. First, copper must be thickly deposited to make certain thatenough copper is deposited to form a layer that fills the trench region31 and has at least a predetermined thickness over the insulation layer24, taking into account the depth of the trench region 31 and contacthole region 30, and the parameters of the chemical mechanical polishing(CMP) process. Thus, the amount of copper subject to the polishing islarge. This decreases the throughput of the fabrication processdecreases, and increases fabrication expense.

[0015] Second, as the amount of copper subject to the polishingincreases, the uniformity of the chemical mechanical polishing (CMP)process is degraded. This causes the thickness of a metalinterconnection layer 26 a finally formed in a substrate 15 to varyaccording to its location, which directly affects the reliability andthroughput of the devices.

[0016] Third, when removing the copper layer using the chemicalmechanical polishing (CMP) process, corrosion of the insulation layer 24occurs according to the density of a metal interconnection layerpattern. This also causes the thicknesses of the metal interconnectionlayers 26 a in a substrate 15 to vary, which, as noted above, results indefects.

[0017] Fourth, different slurries must be used when polishing a seedlayer 24 and a diffusion prevention layer 22 when the seed layer 24 andthe diffusion prevention layer 22 have different polishing speeds. Thiscomplicates the chemical mechanical polishing (CMP) process andincreases fabrication expense.

[0018] Fifth, in a dual damascene structure, the aspect ratio of acontact hole region 30 is very large, which may result in the formationof a void 32 during electroplating, as shown in FIG. 6. Such a void 32,as shown in FIG. 7, remains as a void defect 32 a on the surface of themetal interconnection layer 26 a after surface planarization, therebydeteriorating the reliability of the resulting devices.

SUMMARY OF THE INVENTION

[0019] It is a first objective of the present invention to provide amethod of forming a metal interconnection using a plating process, whichcan improve the throughput and reliability of semiconductor devices bydecreasing the required polishing in a chemical mechanical polishing(CMP) process.

[0020] It is a second objective of the present invention to provide asemiconductor device, which decreases the variation in the thicknessesof metal interconnection layers in a given substrate, and removes voiddefects, thereby improving the reliability of the device.

[0021] To achieve the first objective, the present invention provides amethod of forming a metal interconnection. This method comprises formingan insulation region on a substrate; forming a recess region in theinsulation layer; forming a diffusion prevention layer over insulationlayer and the recess region; forming a metal seed layer over thediffusion prevention layer only in the recess region; and forming aconductive plating layer on the seed layer using plating process.

[0022] The recess region may comprise a trench region of a line shapehaving a predetermined depth from a top surface of the insulation layer.The recess region, may also comprise a trench region of a line shapehaving a predetermined depth from the surface of the insulation layer;and a contact hole region passing through the insulation layer.

[0023] Forming the metal seed layer may further comprise forming apreliminary seed layer over the diffusion prevention layer; and removinga first portion of the preliminary seed layer outside of the recessregion such that a second portion of the preliminary seed layer in therecess region forms the metal seed layer. Forming the preliminary seedlayer is preferably performed by a physical vapor deposition (PVD)method or a chemical vapor deposition (CVD) method.

[0024] Removing a first portion of the preliminary seed layer ispreferably performed by a chemical mechanical polishing (CMP) process.The slurry used for the chemical mechanical polishing (CMP) processpreferably does not contain abrasives. The chemical-mechanical polishing(CMP) process preferably uses a slurry having a polishing selectionratio of 10:1-1000:1 with respect to the preliminary seed layer and thediffusion prevention layer.

[0025] Removing a first portion of the preliminary seed layer preferablyleaves the second portion of the preliminary seed layer and a thirdportion of the preliminary seed layer in the recess region. In addition,the method may further comprise performing a wet etching process on thethird portion of the preliminary seed layer to remove the third portionof the seed layer from the recess region. The wet etching process ispreferably time-controlled.

[0026] The second portion of the preliminary seed layer is preferablyformed only on a bottom surface of the recess region.

[0027] Removing a first portion of the preliminary seed layer mayfurther comprise forming an intermediate material layer over thepreliminary seed layer to fill the recess region; etching back andremoving a first portion of the intermediate material layer and thefirst portion of the preliminary seed layer until a portion of thediffusion prevention layer outside the recess region is exposed; andremoving a second portion of the intermediate material layer remainingin the recess region. The intermediate material layer preferablycomprises a photoresist material.

[0028] The method may further comprise performing a surfaceplanarization process on the conductive plating layer and the diffusionprevention layer to expose a top surface of the insulation layer and toform a metal interconnection layer in the recess region. The surfaceplanarization is preferably performed by a chemical mechanical polishingprocess using a slurry having nearly the same polishing speeds withrespect to the diffusion prevention layer and the plating layer.

[0029] To achieve the second objective, the present invention provides asemiconductor device including a substrate; an insulation layer formedover the substrate, the insulation layer having a recess region isformed in it; a diffusion prevention layer formed over the insulationlayer and in the recess region; a metal seed layer formed over thediffusion prevention layer and in the recess region; and a metalinterconnection layer formed in the recess region on the metal seedlayer therein.

[0030] The recess region preferably comprises a trench region of a lineshape having a predetermined depth from the surface of the insulationlayer, and the metal seed layer is formed over a bottom portion of thetrench region.

[0031] The semiconductor device may further comprising a lowerconductive layer formed over the substrate. The recess region maycomprises a contact hole region that passes through the insulation layerand exposes the lower conductive layer. In this case, the diffusionprevention layer is preferably formed in the contact hole region andover the lower conductive layer, and the metal seed layer is preferablyformed over the bottom portion of the contact hole.

[0032] The recess region may further comprise a trench region of a lineshape having a predetermined depth from the surface of the insulationlayer. In this case, the metal seed layer is preferably formed over abottom portion of the contact hole and a bottom portion of the trenchregion.

[0033] The diffusion prevention layer preferably comprises a materialselected from the group consisting of a tantalum (Ta), tantalum nitride(TaN), tantalum aluminum nitride (TaAlN), tantalum silicon nitride(TaSiN), tantalum silicide (TaSi₂), titanium (Ti), titanium nitride(TiN), titanium silicon nitride (TiSiN), tungsten nitride (WN), cobalt(Co), cobalt silicide (CoSi₂), and a composite layer comprising at leasttwo of these materials. The metal seed layer preferably comprises amaterial selected from the transition metal group of copper, platinum,palladium, rubidium, strontium, rhodium, and cobalt. Preferably, themetal seed layer and the metal interconnection layer both comprisecopper.

[0034] According to the present invention, the plating layer is formedonly in the recess region in which the metal interconnection layer willbe formed so that the plating layer does not have to be formed anythicker than needed, thus greatly reducing the amount of metal to bepolished during a subsequent CMP process. This improves fabricationthroughput and decreases fabrication expense.

[0035] In addition, since the amount of the plating layer to be polishedby the polishing process is small, the uniformity of the CMP process ina given substrate is excellent, which decreases the variation in thethicknesses of the metal interconnection layers formed in the substrate.Moreover, this can prevent dishing or corrosion of the insulation layerbecause the polishing process does not need to be excessively performed.

[0036] Furthermore, the fabrication process is simplified by allowingthe use of a slurry having nearly the same polishing speed with respectto the plating layer and the diffusion prevention layer when polishingthe plating layer and the diffusion prevention layer.

[0037] Moreover, the seed layer on the sidewalls of the recess region isremovedby a wet etching process, which decreases the aspect ratio of therecess region. This improves the gap-filling performance of the platinglayer, thereby preventing void defects. Consequently, this improves thereliability of the resulting semiconductor devices.

BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above objectives and advantages of the present invention willbecome more apparent by describing in detail preferred embodimentsthereof with reference to the attached drawings in which:

[0039]FIGS. 1 through 3 are sectional views showing a method of forminga metal interconnection in a semiconductor device having a conventionalline damascene structure;

[0040]FIGS. 4 through 7 are a plan view and section views showing amethod of forming a metal interconnection in a semiconductor devicehaving a conventional dual damascene structure;

[0041]FIGS. 8 through 10 are sectional views showing a method of forminga metal interconnection in a semiconductor device having a linedamascene structure according to a first preferred embodiment of thepresent invention;

[0042]FIGS. 11 through 13 are sectional views showing a method offorming a metal interconnection in a semiconductor device having a linedamascene structure according to a second preferred embodiment of thepresent invention;

[0043]FIGS. 14 through 16 are sectional views showing a method offorming a metal interconnection in a semiconductor device having a dualdamascene structure according to a third preferred embodiment of thepresent invention; and

[0044]FIGS. 17 through 19 are sectional views showing a method offorming a metal interconnection in a semiconductor device having a dualdamascene structure according to a fourth preferred embodiment of thepresent invention.

DETAILED DESCRIPTION OF THE INVENTION

[0045] The present invention will now be described in greater detailwith reference to the accompanying drawings, in which preferredembodiments of the invention are shown. This invention may, however, beembodied in many different forms and should not be construed as beinglimited to the embodiments set forth herein; rather, these embodimentsare provided so that this disclosure will be thorough and complete, andwill fully convey the concept of the invention to those skilled in theart.

[0046] First Preferred Embodiment

[0047]FIGS. 8 through 10 are sectional views showing a method of forminga metal interconnection according to a first preferred embodiment of thepresent invention. The first preferred embodiment is related to a methodof forming a metal interconnection having a conventional line damascenestructure described in FIGS. 1 through 3. As a result, similar elementsare represented by the same reference numerals in these drawings.

[0048] Referring to FIG. 8, a trench region 11 is formed as a recessregion in an insulation layer 10 over a substrate 5. A diffusionprevention layer 12 and a seed layer 14 are then sequentially formedover the entire surface of the substrate 5, including the trench area11. Next, the seed layer 14 is removed so that it remains only in thetrench area 11.

[0049] Although the drawing shows the insulation layer 10 formeddirectly over the substrate 5, an underlying layer or layers that have aconductivity or an insulating characteristic may be formed between thesubstrate 5 and the insulation layer 10.

[0050] More specifically, the insulation layer 10 may comprise siliconoxide, and may be formed over the substrate 5 and be etched by a typicalphotolithography process to form the trench region 11 in a recessregion. The depth of the trench region 11 is preferably between1000-30,000 Å.

[0051] In one method of forming the trench region 11, a silicon nitridefilm having an etching selectivity with respect to the silicon oxidelayer is deposited over the silicon oxide layer formed on the insulationlayer 10 to form an etching mask layer. The etching mask layer is thencoated with a photoresist layer. A photoresist pattern and a siliconnitride film pattern are formed by a photolithography process and usedfor forming the trench region 11.

[0052] In another method, a photoresist layer may be immediately formedover the insulation layer 10, and then the trench region 11 may beformed by a direct photolithography process.

[0053] After the trench region 11 is formed, a diffusion preventionlayer 12 is formed over the insulation layer 10 and in the trench region11. The diffusion prevention layer 12 acts to improve adhesion to asucceeding interconnection metal and t prevent diffusion of the metalinto the insulation layer 10.

[0054] The diffusion prevention layer 12 may comprise a tantalum (Ta)layer, a tantalum nitride (TaN) layer, a tantalum aluminum nitride(TaAlN) layer, a tantalum silicon nitride (TaSiN) layer, a tantalumsilicide (TaSi₂) layer, a titanium (Ti) layer, a titanium nitride (TiN)layer, a titanium silicon nitride (TiSiN) layer, a tungsten nitride (WN)layer, a cobalt (Co) layer, a cobalt silicide (CoSi₂) layer, or acomposite layer including at least two of these materials. The thicknessof the diffusion prevention layer 12 is preferably between 100-1000 Å.

[0055] Subsequently, the seed layer 14 for plating is formed over theentire surface of the diffusion prevention layer 12. The seed layer 14may comprise a transition metal such as platinum, palladium, rubidium,strontium, rhodium, or cobalt, or may simply comprise copper. The seedlayer is preferably formed to a thickness between 500-5,000 Å.

[0056] In forming the seed layer 14, a physical vapor deposition (PVD)method such as sputtering or a chemical vapor deposition (CVD) methodmay be used. When the CVD method is used, a material is relativelyuniformly deposited over the surface, i.e., the vertical and horizontalsurfaces, of the seed layer 14. In contrast, when the PVD method isused, a material is deposited more thickly on the horizontal surface ofthe seed layer 14 than on the vertical surface parallel to the movingdirection of the deposited material. This is caused by the directionalproperties of the deposited material.

[0057] The portion of the seed layer 14 outside of the trench region 11is then selectively removed so that the seed layer 14 remains only inthe trench region 11. This has the result of exposing the diffusionprevention layer 12, as shown in FIG. 8. One of the following twopreferred methods may be used in selectively removing the seed layer 14.

[0058] The first preferred method uses a chemical mechanical polishing(CMP) process. In the CMP process, a given substrate is loaded into apolishing apparatus, the surface of the substrate, i.e., the top layers,to be polished is brought into contact with a pad provided in thepolishing apparatus, a slurry is applied between the substrate and thepad, and the substrate and the pad are then rotated in oppositedirections. During this polishing process, the height of the surface tobe polished remains uniform.

[0059] When a CMP process is used in this embodiment, the portion of theseed layer 14 outside the trench region 11 contacts the pad of apolishing apparatus during the polishing process, and the process isperformed until only the seed layer 14 within the trench region 11remains. It is preferable that the slurry used for such a CMP processnot include abrasives to prevent a slurry residue from remaining in thetrench region 11 after the CMP process. The CMP process is preferablyperformed using a slurry having a polishing selection ratio of the seedlayer 14 to the diffusion prevention layer 12 of about 10:1-1000:1.

[0060] The second method uses an etch back process. In an etch backprocess, the entire surface of a substrate exposed to an etchingatmosphere is removed at a nearly uniform etching rate. Accordingly, anintermediate material layer may be used in this embodiment of thepresent invention to selectively remove the seed layer 14. In otherwords, an intermediate material layer having an excellent reflowcharacteristic, for example, a photoresist layer, may be thickly formedover the entire surface of the substrate including the trench region 11,and an etch back process performed on the resultant structure. Thephotoresist layer formed over the substrate 5 and the seed layer 14outside the trench region 11 are sequentially etched by the etch backprocess.

[0061] The etch back process is performed until the diffusion preventionlayer 12 outside the trench region 11 is exposed. Then the portion ofthe photoresist layer remaining in the trench region 11 is removed, forexample, by an ashing process, so that only the seed layer 14 in thetrench region 11 remains, as shown in FIG. 8.

[0062] Referring to FIG. 9, the resultant structure shown in FIG. 8 isloaded into a plating apparatus (not shown) containing a platingsolution, and a plating process is performed to form a plating layer 18in the trench region 11, over the seed layer 14. In this preferredembodiment of the present invention, copper is used for the platinglayer, although any conductive metal material that will allow for aplating process may also be used.

[0063] For the plating process used in this embodiment, either anelectroplating method or an electroless plating method can be used. Forexample, in a copper electroplating method, the substrate 5 includingthe seed layer 14 is put into an electrolyte including copper ions, anda voltage is applied to the substrate 5, which is defined as a cathode.Then, the copper plating layer 18 is selectively formed only on the seedlayer 14.

[0064] Alternatively, in an electroless plating method, pretreatment,for example, palladium treatment, is performed on the substrate 5,including the seed layer 14, and the resultant structure is put into aplating solution including copper ions. Then, the copper plating layer18 is selectively formed on only the seed layer 14. In either case, aplating process is performed until the plating layer 18 sufficientlyfills the trench region 11.

[0065] Referring to FIG. 10, the entire surface of the structure is thenplanarized to leave a metal interconnection layer 18 a only in thetrench region 11. For the planarization, a CMP process or an etch backprocess can be performed, as described above. When a CMP process isperformed, the surface of the substrate may be planarized either in asingle step using a slurry having nearly the same polishing selectionratios with respect to the plating layer 18 and the diffusion preventionlayer 12, or using separate processes that are applied to the platinglayer 18 and the diffusion prevention layer 12 individually.

[0066] Second Preferred Embodiment

[0067]FIGS. 11 through 13 are sectional views showing a method offorming a metal interconnection according to a second preferredembodiment of the present invention. Like the first embodiment, thesecond embodiment is related to a method of forming a metalinterconnection having a line damascene structure, as described in FIGS.1 through 3. As a result, in the second preferred embodiment, elementsthat are similar to those in the first preferred embodiment arerepresented by the same reference numerals in the drawings.

[0068] Referring to FIG. 11, an insulation layer 10 is initially formedover a substrate 5. A trench region 11 is then formed at a recess regionin the insulation layer 10. A diffusion prevention layer 12 and a seedlayer 14 are then sequentially formed over the entire surface of thesubstrate 5, including the trench area 11. Finally, the seed layer 14 isremoved so that it remains only in the bottom portion of the trench area11.

[0069] Fundamentally the same processes as those of the first preferredembodiment are applied to the second preferred embodiment with theexception that a larger portion of the deposited seed layer 14 isremoved such that it remains only in the bottom portion of the trenchregion 11. In this embodiment particularly, it is preferable to use aPVD method, such as sputtering (described above), in forming the seedlayer 14. This is because in a PVD method, material is deposited morethickly on a horizontal surface of a layer (perpendicular to the movingdirection of the deposited material) than on a vertical surface(parallel to the moving direction of the deposited material) as a resultof the directional properties of the deposited material

[0070] More specifically, when a wet etching process is performed on thesubstrate to remove the portions of the seed layer 14 not in the bottomportion and on the sidewalls of the trench region 11 as shown in FIG. 8,some portion of the seed layer in the trench region will be removed ifthe seed layer 14 is relatively thinly formed on the sidewalls of thetrench region 11, then it may be completely removed, while if the seedlayer 14 is relatively thickly formed in the bottom portion of thetrench region 11 it will remain after a predetermined time has passed.

[0071] When performing the wet etching process, an etchant suitable forthe feature of the seed layer 14 can be used. For example, when the seedlayer 14 is formed of copper, an etchant obtained by diluting sulfuricacid and hydrogen peroxide with ultra pure water may be used. The wetetching process is preferably performed over a controlled period of timesuch that a portion of the seed layer 14 remains in the bottom portionof the trench region 11, while the seed layer 14 is completely removedfrom the sidewalls of the trench region 11.

[0072] Referring to FIG. 12, in an manner similar to that of the firstpreferred embodiment, the resultant structure shown in FIG. 11 is loadedinto a plating apparatus (not shown) containing a plating solution, anda plating process is performed to form a plating layer 19 in the trenchregion 11 over the seed layer 14. However, unlike the first preferredembodiment, the seed layer 14 does not exist on the sidewalls of thetrench region 11 in this embodiment. Accordingly, the aspect ratio ofthe trench region 11 is low enough that the plating layer 19 can besatisfactorily formed without forming a void. Preferably the platinglayer 19 is formed to sufficiently fill the trench region 11.

[0073] Referring to FIG. 13, the entire surface of the substrate,including the plating layer 19 and the diffusion prevention layer 12 isplanarized to form a metal interconnection layer 19 a only in the trenchregion 11. As described above with respect to the first preferredembodiment, a CMP process or an etch back process described before canbe performed to achieve this planarization. When a CMP process isperformed, it is preferable that the surface of the substrate beplanarized in one step using slurry having nearly the same polishingselection ratios with respect to the plating layer 19 and the diffusionprevention layer 12.

[0074] Third Preferred Embodiment

[0075]FIGS. 14 through 16 are sectional views that show a method offorming a metal interconnection according to a third preferredembodiment of the present invention. The third preferred embodiment issimilar in some ways to a method of forming a metal interconnectionhaving a conventional dual damascene structure, as described in FIGS. 4through 7. As a result, similar elements are represented by the samereference numerals in these drawings.

[0076] Referring to FIG. 14, a lower conductive layer 28 and aninsulation layer 20 are sequentially formed over a substrate 15. Acontact hole region 30 and a trench region 31 then formed in theinsulation layer 20 as a recess region, thereby forming a dual damascenestricture. The contact hole region 30 is formed to expose the surface ofthe lower conductive layer 28 on the substrate. The trench region 31 iscombined with the contact hole region 30 and together they form a lineshape having a predetermined depth from the surface of the insulationlayer 20. A diffusion prevention layer 22 and the seed layer 24 aresequentially formed on the entire surface of the substrate having therecess region, and then the seed layer 24 on the insulation layer 20 isremoved so that the seed layer remains only in the recess region.

[0077] As in the first preferred embodiment, although the insulationlayer 20 is shown as being formed directly over the substrate 15, one ormore additional layers having a conductivity or an insulatingcharacteristic may be formed between the insulation layer 20 and thesubstrate 15.

[0078] The depth of the trench region is preferably between 1000-30,000Å. The diffusion prevention layer 22 may comprise a tantalum (Ta) layer,a tantalum nitride (TaN) layer, a tantalum aluminum nitride (TaAlN)layer, a tantalum silicon nitride (TaSiN) layer, a tantalum suicide(TaSi₂) layer, a titanium (Ti) layer, a titanium nitride (TiN) layer, atitanium silicon nitride (TiSiN) layer, a tungsten nitride (WN) layer, acobalt (Co) layer, a cobalt silicide (CoSi₂) layer, or a composite layerincluding at least two of these materials. The thickness of thediffusion prevention layer 22 is preferably between 100-1000 Å.

[0079] The seed layer 24 is preferably made of copper, but may also beformed of a transition metal such as platinum, palladium, rubidium,strontium, rhodium, or cobalt. The seed layer 14 is preferably formed toa thickness of about 500-5,000 Å. The seed layer 24 may be formed by aPVD method, such as sputtering, or a CVD method.

[0080] After the seed layer 24 is deposited, a CMP process or an etchback process may be used to expose the diffusion prevention layer 22, asdescribed above with respect to the first preferred embodiment. The CMPprocess or an etch back process will selectively remove a portion of theseed layer 24 outside of the recess region, allowing the seed layer 24to remain only in the recess region, as shown in FIG. 14. Preferably, ifa CMP Process is used, the slurry does not include abrasives asdescribed with respect to the first preferred embodiment.

[0081] Referring to FIG. 15, the resultant structure shown in FIG. 14 isthen loaded into a plating apparatus (not shown) containing a platingsolution, and a plating process is performed to form a plating layer 27only in the recess region, which has the seed layer 24. In thisembodiment, either an electroplating method or an electroless platingmethod can be used for the plating process. The plating process ispreferably performed until the plating layer 27 fills the recess region,as shown in FIG. 15.

[0082] Referring to FIG. 16, the entire surface of the substrate,including the plating layer 27 and the diffusion prevention layer 22 isplanarized such that a metal interconnection layer 27 a remains only inthe recess region. For the planarization, a CMP process or an etch backprocess described before can be performed. When a CMP process isperformed, the surface of the substrate is preferably planarized in asingle step, using a slurry having nearly the same polishing selectionratios with respect to the plating layer 27 and the diffusion preventionlayer 22.

[0083] Fourth Preferred Embodiment

[0084]FIGS. 17 through 19 are sectional views that show a method offorming a metal interconnection according to a fourth preferredembodiment of the present invention. Like the third preferredembodiment, the fourth preferred embodiment is related to a method offorming a metal interconnection having a dual damascene structure. Thisembodiment is similar to the third preferred embodiment of FIG. 14, andso similar elements are represented by the same reference numerals inthe drawings.

[0085]FIG. 17 is a sectional view of the structure obtained byperforming a wet etching process on a structure a seed layer 24 only inthe recess region as shown in FIG. 14. Fundamentally, the same processesas those of the third preferred embodiment are applied to thisembodiment, with the exception that the seed layer 24 remains only inthe bottom portion, i.e., the horizontal surface, of the recess region,as opposed to the sides as well.

[0086] In this embodiment, it is preferable to use a PVD method, such assputtering, to form the seed layer 24 (as described above). The PVDmethod is preferable because it deposits material more thickly on thehorizontal surface of a layer than on the vertical surface parallel tothe moving direction of the deposited material. This is because of thedirectional properties of the deposited material.

[0087] Because of this, a wet etching process can be used to provide thestructure shown in FIG. 17. After performing the PVD method to depositthe seed layer on the substrate, the seed layer 24 is formed on both thebottom portion and the sidewalls of the recess region, including thecontact hole 30 and the trench region 31, as shown in FIG. 4. However,the seed layer 24 is formed relatively thinly on the sidewalls of therecess region, but is formed much more thickly on the bottom portion ofthe recess region. As a result, after a predetermined etching duration,the seed layer 24 is completely removed from the side wall, but remainson the bottom surfaces of the contact hole 30 and trench region 31.

[0088] The wet etching process is preferably performed by controllingthe etching time such that a portion of the seed layer 24 remains in thebottom portion of the recess region, but the portion of the seed layer24 on the sidewalls of the recess region is completely removed. However,in alternate embodiments, the etching time of the wet etching precessmay be controlled such that a portion of the seed layer 24 remains onthe sidewalls of the recess region.

[0089] Referring to FIG. 18, as in the third preferred embodiment, theresultant structure shown in FIG. 17 is loaded into a plating apparatus(not shown) that contains a plating solution, and a plating process isperformed to form a plating layer 29 in the recess region, whichcontains the seed layer 24. Unlike the third preferred embodiment,however, in this embodiment, no portion of the seed layer 24 remains onthe sidewalls of the recess region. Accordingly, the aspect ratio of therecess region is low, meaning that the plating layer 29 can besatisfactorily formed without forming a void.

[0090] Referring to FIG. 19, the entire surface of the substrate is thenplanarized to form a metal interconnection layer 29 a that is only inthe recess region. For the planarization, a CMP process or an etch backprocess can be performed as described above. If a CMP process isperformed, it is preferable that the surface of the substrate isplanarized in a single step using a slurry having nearly the samepolishing selection ratios with respect to the plating layer 29 and thediffusion prevention layer 22.

[0091] While this invention has been particularly shown and describedwith reference to preferred embodiments thereof, it will be understoodby those skilled in the art that various changes in form and details maybe made therein. In particular, the present invention can be applied toa line damascene structure and a dual damascene structure and alsoapplied to formation of a plug filling a contact hole or a via-hole in asingle shape. In addition, various materials can be used for forming aplating layer as long as the material allows a plating process.

[0092] According to the present invention, first, a plating layer isformed only in a recess region in which a metal interconnection layerwill be formed so that the plating layer does not have to be formedthicker than needed and the amount of metal to be polished during asubsequent CMP process or an etch back process can be greatly reduced.This improves throughput and decreases fabrication expense.

[0093] Second, since the amount of the plating layer to be polished bythe polishing process is small, the uniformity of the polishing processin a given substrate is excellent, which can decrease the variation inthe thicknesses of metal interconnection layers formed in the substrate.Moreover, this can prevent dishing or corrosion of the insulation layerbecause the polishing process does not need to be performed excessively,thereby improving the reliability of semiconductor devices.

[0094] Third, since a seed layer does not remain outside the recessregion, the same slurry can be used with respect to the plating layerand a diffusion prevention layer during a CMP process, thus simplifyingthe fabrication process.

[0095] Fourth, even if the seed layer remaining on the sidewalls of therecess region is removed, the plating layer can be sufficiently formed.Accordingly, the aspect ratio of the recess region can be sufficientlylow that the gap-filling performance of the plating layer is improved.Consequently, the reliability of semiconductor devices can be improved.

What is claimed is:
 1. A method of forming a metal interconnection, themethod comprising: forming an insulation region on a substrate; forminga recess region in the insulation layer; forming a diffusion preventionlayer over insulation layer and the recess region; forming a metal seedlayer over the diffusion prevention layer only in the recess region; andforming a conductive plating layer on the seed layer using platingprocess.
 2. A method of forming a metal interconnection, as recited inclaim 1, wherein the recess region comprises a trench region of a lineshape having a predetermined depth from a top surface of the insulationlayer.
 3. A method of forming a metal interconnection, as recited inclaim 1, wherein the recess region, comprises: a trench region of a lineshape having a predetermined depth from the surface of the insulationlayer; and a contact hole region passing through the insulation layer.4. A method of forming a metal interconnection, as recited in claim 1,wherein forming the metal seed layer further comprises: forming apreliminary seed layer over the diffusion prevention layer; and removinga first portion of the preliminary seed layer outside of the recessregion such that a second portion of the preliminary seed layer in therecess region forms the metal seed layer.
 5. A method of forming a metalinterconnection, as recited in claim 4, wherein forming the preliminaryseed layer is performed by a physical vapor deposition (PVD) method or achemical vapor deposition (CVD) method.
 6. A method of forming a metalinterconnection, as recited in claim 4, wherein removing a first portionof the preliminary seed layer is performed by a chemical mechanicalpolishing (CMP) process.
 7. A method of forming a metal interconnection,as recited in claim 6, wherein a slurry used for the chemical mechanicalpolishing (CMP) process does not contain abrasives.
 8. A method offorming a metal interconnection, as recited in claim 6, wherein thechemical-mechanical polishing (CMP) process uses a slurry having apolishing selection ratio of 10:1-1000:1 with respect to the preliminaryseed layer and the diffusion prevention layer.
 9. A method of forming ametal interconnection, as recited in claim 4, wherein removing a firstportion of the preliminary seed layer leaves the second portion of thepreliminary seed layer and a third portion of the preliminary seed layerin the recess region, and further comprising performing a wet etchingprocess on the third portion of the preliminary seed layer to remove thethird portion of the seed layer from the recess region.
 10. A method offorming a metal interconnection, as recited in claim 9, wherein the wetetching process is time-controlled.
 11. A method of forming a metalinterconnection, as recited in claim 10, wherein the second portion ofthe preliminary seed layer is formed only on a bottom surface of therecess region.
 12. A method of forming a metal interconnection, asrecited in claim 4, wherein removing a first portion of the preliminaryseed layer further comprises: forming an intermediate material layerover the preliminary seed layer to fill the recess region; etching backand removing a first portion of the intermediate material layer and thefirst portion of the preliminary seed layer until a portion of thediffusion prevention layer outside the recess region is exposed; andremoving a second portion of the intermediate material layer remainingin the recess region.
 13. A method of forming a metal interconnection,as recited in claim 12, wherein the intermediate material layercomprises a photoresist material.
 14. A method of forming a metalinterconnection, as recited in claim 1, further comprising performing asurface planarization process on the conductive plating layer and thediffusion prevention layer to expose a top surface of the insulationlayer and to form a metal interconnection layer in the recess region.15. A method of forming a metal interconnection, as recited in claim 14,wherein the surface planarization is performed by a chemical mechanicalpolishing process using a slurry having nearly the same polishing speedswith respect to the diffusion prevention layer and the plating layer.16. A semiconductor device comprising: a substrate; an insulation layerformed over the substrate, the insulation layer having a recess regionis formed in it; a diffusion prevention layer formed over the insulationlayer and in the recess region; a metal seed layer formed over thediffusion prevention layer and in the recess region; and a metalinterconnection layer formed in the recess region on the metal seedlayer therein.
 17. A semiconductor device, as recited in claim 16,wherein the recess region comprises a trench region of a line shapehaving a predetermined depth from the surface of the insulation layer,and the metal seed layer is formed over a bottom portion of the trenchregion.
 18. A semiconductor device, as recited in claim 16, furthercomprising a lower conductive layer formed over the substrate, whereinthe recess region comprises a contact hole region that passes throughthe insulation layer and exposes the lower conductive layer, wherein thediffusion prevention layer is formed in the contact hole region and overthe lower conductive layer, and wherein the metal seed layer is formedover the bottom portion of the contact hole.
 19. A semiconductor device,as recited in claim 18, wherein the recess region further comprises atrench region of a line shape having a predetermined depth from thesurface of the insulation layer.
 20. A semiconductor device, as recitedin claim 19, wherein the metal seed layer is formed over a bottomportion of the contact hole and a bottom portion of the trench region.21. A semiconductor device, as recited in claim 16, wherein thediffusion prevention layer comprises a material selected from the groupconsisting of a tantalum (Ta), tantalum nitride (TaN), tantalum aluminumnitride (TaAlN), tantalum silicon nitride (TaSiN), tantalum silicide(TaSi₂), titanium (Ti), titanium nitride (TiN), titanium silicon nitride(TiSiN), tungsten nitride (WN), cobalt (Co), cobalt silicide (CoSi₂),and a composite layer comprising at least two of these materials.
 22. Asemiconductor device, as recited in claim 16, wherein the metal seedlayer comprises a material selected from the transition metal group ofcopper, platinum, palladium, rubidium, strontium, rhodium, and cobalt.23. A semiconductor device, as recited in claim 22, wherein the metalseed layer and the metal interconnection layer both comprise copper.